Our partner have a question about i.MX6S eCSPI.
If the garbage data is stored when starting the transmit or receive operations, we think unexpected operation will be occurred.
So, we want to clear it forcibly.
Would you let me know how to clear both transmit data (transmit FIFO & shift register) and received data (receive FIFO & shift register) forcibly ?
And let me know whether the procedure is different between master and slave mode also?