Hello,Community
I am now working with i.MX6.
I want to input YUV data in UYVY format to CSI0 via parallel interface through an 8-bit bus,
and the max clock frequency is to be set to 100MHz.Besides,the synchronous signals will be
V-sync and H-sync.
In this case, I believe I just need to set the CSI0 Sensor Configuration Register(IPUx_CSI0_SENS_CONF)
as below.
1)set CSI0_SENS_DATA_FORMAT field to 010b(select UYVY format).
2)set CSI0_DATA_WIDTH field to 0001b(select 8 bit mode).
3)set CSI0_DATA_DEST field to 010b(select dest SMFC).
Could you let me know whether my understanding is right?
Or need I do something else to implement my idea?
Best Regards,
ZongbiaoLiao
Hi 宗標
you can look for supported formats at
IMX6DQCEC Table 66. Camera Input Signal Cross Reference, Format, and Bits Per Cycle
Best regards
igor
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Hello,igorpadykov
Thank you for your answer.
In my case, the Timing/Data mode protocol is not BT.656, it is Gated mode.
So how should I set the related registers.
Best Regards,
ZongbiaoLiao
Hi 宗標
according to that Table for "YUV data in UYVY format through an 8-bit bus"
possible option only "YCbCr, 8 bits—Supported within the BT.656 protocol (sync
embedded within the data stream)".
So "Gated mode" is not supported.
~igor
Hello,igorpadykov
I did a test on i.MX6dlsabresdp(which with an ov5642 camera equipped).
After running /unit_test/mxc_v4l2_capture.out with proper parameters,
I read the CSI0 Sensor Configuration Register(IPU_CSI0_SENS_CONF)
and value for this register was 0x8900.
According to this value,configurations for CSI0 is as below:
1)data width is 8-bit
2)data format is YUV422 (YUYV...)
3)Timings mode is Gated mode.
So, if my understanding of IPU_CSI0_SENS_CONF register is right,
then I can refer to i.MX6dlsabresdp to resolve my problem.
Could you let me know whether is my understanding right or not?
Best Regards,
ZongbiaoLiao
Hi ZongbiaoLiao
datasheet gives recommended by Freescale formats.
Their operation is guaranteed and tested, this is described
in official datasheet IMX6DQCEC Table 66. Camera Input Signal
Cross Reference, Format, and Bits Per Cycle
You can find also some experimental efforts, however
you can use them on own risk.
~igor
Looking at Table 66, can we use YCbCr7 16 bits 1 cycle, gated mode, C[0]-C[7] mapped to DATA02-DATA09 (second to last column), is that possible, or does it require embedded sync?
If not, we would like to use gated mode YCbCr, preferably 1 cycle. Is generic data (no on the fly processing) the only option for 1 cycle gated mode?
Best regards,
Aaron
Hello igor
Thank you for your answer.
Do you mean i.MX6 support Gated mode, but it may have risks?right?
I donnot know what kinds of risks would happen.I just want to refer to i.MX6dlsabresdp
to implement gated mode.
Could you kindly give me some prompts.
Best Regards,
ZongbiaoLiao
Hi ZongbiaoLiao
sorry, I am not aware of any codes supporting
this case
~igor