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Strange behaviour in DSC´s ADC12

Question asked by Carlos Barcala on Feb 4, 2015
Latest reply on Feb 13, 2015 by Carlos Barcala

Hi everybody,

 

I´m using DSC56F84789 + CW10.4 + ProcessorExpert to develop a project that samples several channels of the ADC12 (triggered parallel, converter A only, simultaneous). I can see random samples that are close to (or exactly at) 16384, when the sampled signal is a sinusoidal ranged from +5000 to -5000, 50 Hz which a sampling frequency of 6400 Hz. Sampling is perfet appart from these sporadic (once a day, once in a weekend, twice a day...) outliers.

 

Has anyone experienced a similar problem?

 

As I know there´s a bug in PE that generates wrong configuration of ADC, I manually setup up the ADC12 registers like this:

 

setRegBit(ADC12_CTRL1,STOP0);      //0x4000: Stop command issued

 

 

setRegBit(ADC12_PWR,APD);//Activa autoapagado
clrRegBits(ADC12_PWR2,ADC12_PWR2_SPEEDA_MASK);//relojA <5MHz
setRegBitGroup(ADC12_CTRL1,SMODE,0b101);//0x0005: triggered parallel
setRegBit(ADC12_CTRL1,EOSIE0);//0x0800: ADCA EOSI0 interrupt enabled
setRegBit(ADC12_CTRL1,SYNC0);//0x1000: ADCA Triggered by SYNC0 pulses

 

 

clrRegBit(ADC12_CTRL2,SIMULT);//0x0000: Independent
setRegBitGroup(ADC12_CTRL1,CHNCFG_L,0x03);//0x0030
setRegBitGroup(ADC12_CTRL2,CHNCFG_H,0x03);//0x00B0

 

 

clrRegBit(ADC12_CTRL1,STOP0);      /* Stop command cleared */

 

 

Best regards

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