LPDDR2 config on imx6sl

[tony_l_cai]

Hi,All

     Maybe, some params in LPDDR2 Aid is not right,so when I use the DDR stress tool, test is failed.

     So I want to know some definition about the options in Aid.

     DRAM single Die density，How to know how many dies is in this LPDDR2. Some datasheet didnt show it clearly.

     Number of chip selects used, How to know in datasheet.  I cant find the clear answers in datasheet,either.

     So could you give me more help,and make Aid can pass the DDR stress test.

     our LPDDR2 is winbond W97BH2KBQX2I，and the LPDDR2 datasheet and Aid settings are following.

     After ddr stress test ，the result is following. I want to know If the DDR can not work??

     Dont to tell me where the DDR controller addr is ,and the following is not. so the DDR settings is not right.

     But before this LPDDR2, we also use a LPDDR2, in inc, the DDR controller addr is the same with this DDR,and the former one can work.

     so I just want to say, maybe some other factors make this DDR can not work. Please help me, thank you very much !  

[igorpadykov]

Hi tony

this LPDDR2 is single die. Error in attached file:

"dcd address 0x020bc000 out of valid address range "

is because WDOG1 should not be in dcd data,

please remove this line ("setmem /16    0x020bc000 =    0x30" in *.inc file).

Valid dcd data addresses are given in

Table 8-29. Valid DCD Address Ranges IMX6SLRM

Best regards

igor

[tony_l_cai]

Hi igor

I have tried what you said,the result is

HAB_TYPE: DEVELOP

rom_write: reading HAB ack failed 0x00000000

ROM Write failed, addr: 0x021b001c

Write dcd failed.

and I know MMDC valid addr start from 0x021B0000,but your Aid can automatically generate the Inc, I cannot motify it because I dont know whether it is right after motifying it.

So could you give me another help? 3q very much!

[igorpadykov]

Hi tony

you can try board SDK (one can run it with jtag) with your ddr settings

and use ddr_test.c (there one can find MX6SL_EVK_LPDDR2_v0.9.inc)

i.MX 6Series Platform SDK

after these simple tests will run OK, one can try DDR test

~igor

[tony_l_cai]

Hi Igor,

     We just have Trace32 in our hands. Can you tell us how to use this SDK with Trace32 or the method to debug this issue with Trace32?

Thanks

Tony

[igorpadykov]

Hi tony

in SDK you will find ../tools/lauterbach

~igor

[Yuri]

  Please look at my comments below.

1.

  Please refer to section 2 (DDR3 initialization Script Generation Aid) of the
Porting Guide for more details regarding Script Generation Aid using.

https://community.freescale.com/servlet/JiveServlet/download/101708-1-278514/Freescale%20i.MX6%20DRA...

https://community.freescale.com/docs/DOC-101708

2.

It looks like two CS(s) and 32-bit data bus are applied in the case.
Is it so (four W97BH2KBQX2I parts) ?  In such case “DRAM density per CS”
is 4 (Gb).

(if possible, please provide connection scheme between i.MX6 SL and DRAMs.)  

3.

  According to the DRAM Datasheet “number of COLUMN addresses” is 10.

4.

You may try to adjust drive strength options.

https://community.freescale.com/thread/338460

Have a great day,
Yuri

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[tony_l_cai]

Hi Yuri,

2. only one w97bh2kbq2i part, why are 4 parts? Where did you get this info about 4 parts?

3. In datasheet,

Column addr C0-C8,so number of Column addr ,why is 10,not 9 ? How to get 10?

发件人: Yuri Muhin

发送时间: 2015年2月5日 16:43

收件人: Tony L Cai

主题: Re: - LPDDR2 config on imx6sl

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LPDDR2 config on imx6sl

reply from Yuri Muhin<https://community.freescale.com/people/Yuri?et=watches.email.thread> in i.MX Community - View the full discussion<https://community.freescale.com/message/477807?et=watches.email.thread#477807>

[Yuri]

Tony,

  I was mistaken with DRAM part number, sorry.
In the same time, in Your file “clipboard.png” number of CS = 2 ; this means

at least two DRAM devices. Please correct it (number of CS).

Regards,

Yuri.