We are using MCIMX6U6AVM10CB in our design with four DRAM memory. While doing post SI analysis using hyperlynx DDR3 wizard for 800MT/s (400MHz clk) all parameters are passing except for max slew time. Max slew time (Tslew_ac) given in ibis model is 140ps where as during data read we are getting worst case Tslew_ac around 177ps. Do we need to consider this as failure if i am getting good setup and hold margin in my simulation. (50ps setup margin, 125ps hold margin).
IBIS model referred- 21x21_imx6q_autmtv_004
ODT setting used in controller during data read- ddr3odt_t120_sel11_mi
Corners failing- all (Fast, typical and slow) with worst result seen in slow corner.
Please find attached JEDEC result spreadsheet and Data spreadsheet for reference.
Could you please correct my understanding regarding maximum slew time restriction. Maximum slew time is maximum rise time allowed for signal to rise from Vil_ac to vih_ac so that setup and hold margins are not violated.
Original Attachment has been moved to: DDR_report_data_allcases_Fast.csv.zip