Hi All,

Refer to Table 2-7. Oscillator and clock recommendations in Hardware Development Guide for i.MX 6, Rev. 1.

There is below description.

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Alternatively, a single-ended signal can be used to

drive a CLKx_P input. In this case, the corresponding

CLKx_N input should be tied to a constant voltage

level equal to 50% of VDD_HIGH_CAP.

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TIA/EIA-644 standard.sect.4.2.4 defines allowable common voltage range as +0.050 V to +2.350 V.

So CLKx_P voltage can be applied to 2.350V.

Which is right voltage for CLKx_N?

1. CLKx_N level equal to 50% of VDD_HIGH_CAP.

(VDD_HIGH_CAP=2.5V, so CLKx_N=1.25V)

2. CLKx_N level equal to 50% of CLKx_P.

(CLKx_P=2.35V, so CLKx_N=1.175V)

Best Regards,

Keita

Hi Keita

both options are right, however

if CLKx_N,P is used for providing reference clock

one needs try to produce duty cycle close to 50%

(this will depend on CLKx_N level and voltage swing

on CLKx_P (this will depend on loading)).

Just for reference one can look at Vybrid DPLL duty cycle

(i.MX6 has the same DPLLs) Table 68 "PLL1 and PLL2 Electrical Parameters"

and others.

http://cache.freescale.com/files/microcontrollers/doc/data_sheet/VYBRIDFSERIESEC.pdf

Best regards

igor

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