Is there any way to reset the timer status register WRS bits, other than resetting the whole core in the P4080?
I don't think so, because the e500mc Core Reference Manual says at page 59
This change prevents software from clearing a watchdog time-out that should result in the action defined
in TCR[WRC], in which these bits are reflected into the TSR[WRS] when the watchdog times out. Without
this change, it is theoretically possible that these bits could be cleared prior to the SoC seeing the bits
change, causing the watchdog action to fail.
And if this is not possible, is it possible to signal a Watchdog Timeout to other cores multiple times?
Thanks for your help.