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T042 PLL not locking - set to "kill" in status registers

Question asked by Dan Fitzgerald on Feb 3, 2015
Latest reply on Jul 5, 2017 by Doron Shaanan

Hi All - Has anyone seen Platform, DDR, Core complex clocks all showing the "kill" bit set in their respective status registers?  We have a valid single ended SYSCLK, which is used to clock in the RCW, and ASLEEP is driven low, but after the RCW init phase, the internal multipliers are not working and the 100MHz SYSCLK is being used as the platform clock.  Any clues where to begin looking?

Thanks

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