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Are LP (Low Power) signals necessary on iMX6 Quad MIPI CSI-2 DPHY ?

Question asked by Omar Pighi on Feb 2, 2015
Latest reply on Feb 5, 2015 by igorpadykov

Hi community,


I'm trying to write a new device driver for a camera sensor with MIPI interface connected to iMX6 Quad processor. The sensor has a parallel output data bus that comes into an FPGA that converts parallel data to Mipi serial data.

Has anyone some experience with Low Power signals in mipi?

On TX side, actually, I don't have LP management so I connected clk and data line to gnd by 50ohm resistor following FPGA data sheet for "free run" mode.

Do you know if it's possible to configure iMX6 MIPI CSI-2 in this way? Or CSI-2 needs the LP (Low Power) management with LP11 --> LP01 --> LP00 sequence?


Following some details:


Sensor: Aptina ar0134, 1280x960pix, monocrome 12bit, 54fps

FGPA: Lattice MachXO2 with MIPI CSI-2 Transmit Bridge IP Core

MIPI configuration: 4lane, freeRun (no LP signals management)

Linux driver: ov5640_mipi adapted in I2C configuration, data lane (from 2 to 4) and clock frequency.


Actually sensor is correctly probed and /dev/video0 device is created.

When I try to "cat /dev/video0" this is the consolle output:


root@xxxxx-imx6q:~# cat /dev/video0


ar0134_set_virtual_channel: virtual channel=0

mipi csi2 can not receive sensor clk! 200

ERROR: v4l2 capture: mxc_v4l_read timeout counter 0

cat: /dev/video0: Timer expired

power_down_callback: ipu0/csi0

Many thanks in advance for your support.