Question, i.MX28 DCDC_VDDIO during reset

[Aemj]

Dear team,

I would like to ask about the status of DCDC_VDDIO of i.MX28 during asserting reset.

Is there a specification on the output voltage of DCDC_VDDIO during asserting reset?

On my customer’s board, they measured that DCDC_VDDIO output is about 2V during reset.

They does not use 5V supply input, only 3.3V is fed to DCDC_BATT.

Thanks,

Miyamoto

[Yuri]

  According to section 11.3.3 (Power-Up Sequence) of the i.MX28 Reference Manual:
“the VDDIO, VDDD and VDDA supplies are held at ground. This is the off state that
continues until the system power up begins”. Generally during reset the VDDIO
is not predefined and it is typically set during system initialization.

Next, “when a power-up event has occurred, if VDD5V is valid, then the on-chip linear

  regulators charge the VDDD, VDDA and VDDIO rails to their default voltages”.
Please refer to the section 11.3.3 for more details.
If possible, please provide waveforms of VDD5V, DCDC_BATT, BATT inputs and VDDIO
output.

Have a great day,
Yuri

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