I tried to verify which clock exactly is slected by the SAI bus clock selection (TCR2[MSEL]=0).
Let's start from the obvious: When I set TCR2[MSEL] = 01, I get the clock defined CCM_CSCMR1[SAIn_CLK_SEL], more over the whole logic including the gate CCM_CSCDR1[SAIn_EN] and the divider CCM_CSCDR1[SAIn_DIV] works as documented in Chapter 9.10.12 SAI clocking.
However, when switching to TCR2[MSEL] = 00, unexpectetly the output clock does not change. Also, when I use the gate from above (CCM_CSCDR1[SAIn_EN]) my bit clock gets disabled too, hence it looks like the two MSEL are actually the same SAIn clocks, as configured in CSCMR1 and friends. Is this really the case or am I missing something? IMHO, the documentation is somewhat unclear if Bus Clock actually really selects the SAIn clock too...