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Using Watchdog Interrupt with MPIC in P4080

Question asked by Clemens Reibetanz on Jan 28, 2015
Latest reply on Jan 29, 2015 by Clemens Reibetanz

Hi,

I still struggle to get a watchdog interrupt in P4080.

I want to signal to Core0 that Core4 got a watchdog timeout. I think this is possible with the MPIC.

These are the relevant setting on Core4:

 

TCR=0x98120000

MSR=0x2a000

MPIC_IILR1=0x0

MPIC_IIVPR1=0x88000c

MPIC_IIDR1=0x1

But when an interrupt occurs, this is what I get

Core4: MPIC_WSRSR0=0x0

Core4: TSR=0xf0000000

Core4: InterruptHandler: 0xb00 exception.

 

What I expected was that there is something in the MPIC_WSRSR0.

I also set EDBCR0[EDM] to 0, thanks to lunminliang, but this also didn't help.

 

The manual (P4080RM p. 340)

The platform indicates to the MPIC that a core watchdog timer event has occurred by

updating the core’s associated field (WRSn) in the MPIC's Watchdog Status Register

Summary Register (WSRSR).

 

So what else do I need to do so the WSRSR is updated?

 

Thanks for the help so far.

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