Dear Sir or Madam,
Refer to Table 2-7. Oscillator and clock recommendations in Hardware Development Guide for i.MX 6, Rev. 1.
There is below description.
Alternatively, a single-ended signal can be used to
drive a CLKx_P input. In this case, the corresponding
CLKx_N input should be tied to a constant voltage
level equal to 50% of VDD_HIGH_CAP.
How much is the deviation of the CLKx_N voltage permissible?
Do you have voltage range of CLKx_N?