Dear Sir or Madam,
Hello.
Refer to Table 2-7. Oscillator and clock recommendations in Hardware Development Guide for i.MX 6, Rev. 1.
There is below description.
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Alternatively, a single-ended signal can be used to
drive a CLKx_P input. In this case, the corresponding
CLKx_N input should be tied to a constant voltage
level equal to 50% of VDD_HIGH_CAP.
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How much is the deviation of the CLKx_N voltage permissible?
Do you have voltage range of CLKx_N?
Best Regards,
Keita
Solved! Go to Solution.
Hi Keita
TIA/EIA-644 standard.sect.4.2.4
defines allowable common voltage range as
+0.050 V to +2.350 V . So this voltage can be applied
to CLKx_N.
Best regards
igor
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Hi Keita
TIA/EIA-644 standard.sect.4.2.4
defines allowable common voltage range as
+0.050 V to +2.350 V . So this voltage can be applied
to CLKx_N.
Best regards
igor
-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------