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P1022 - Issue on HRESET while loading Flash

Question asked by Adam Garrison on Jan 26, 2015
Latest reply on Jan 27, 2015 by lunminliang

I have a more hardware related question. In AN4343, the Design Checklist, on page 26, note 7 on Figure 5 says “CKSTP_OUT0,CKSTP_OUT1 are POR muxed with cfg_romloc and may need to be separated.”


Our struggle right now is we have a 4.7k pull down resistor on CKSTP_OUT1 to set the CFG_ROM_LOC during POR. I had left this CKSTP output disconnected from the COP interface and just used the CKSTP0 signal to drive it directly, figuring that the two cores would halt pretty much in sync during reset assertion.


What appears to be happening though is that core 1 is halting a little slower than core 0, and the Codewarrior TAP is reporting that the device is not halted. However, if we probe the HRESET signal, suddenly it thinks the processor is properly halted and proceeds with trying to load the flash.


Our only theory right now is the extra capacitance of the probe is slowing the HRESET signal down just enough that the other core is able to get halted in time for it to work.


So, to come full circle, what we’re trying to do right now is hook up the CKSTP1 signal through an AND gate as per the design checklist, but it requires a pullup resistor because it looks like it’s an open drain output (though I can’t confirm that anywhere) and so I’m trying to balance the value of that pullup between pulling the signal high enough for the AND gate to recognize a logic high, and still have the P1022 recognize the pulldown for POR configuration.


Does any of that make sense? The quoted text at the very top of the email is really confusing to me right now. I’m not sure at all what “may need to be separated” means in a practical sense.