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Problem with PWMA output

Question asked by Pradnya Naik on Jan 23, 2015
Latest reply on Feb 9, 2015 by xiangjun.rong

I am working on MC56F84763 DSC with TWR56F8400 evaluation board.  I am using the PWMA module to generate pulses with 100 µs low pulse and varying high pulse (max value 66 µs).

 

The following steps are performed to generate the pulses:

1) PWMA_Init() function: Initializes PWMA_0A, PWMA_1A, PWMA_2A and PWMA_3A submodules to generate 4 output pulses:     Inverted polarity used.    Independent PWM channels.   

PWMA output enabled.   

Debug mode enabled.   

INIT value initialized to zero. 

VAL0, VAL1, VAL2, VAL4 and VAL5 are initialized to zero.   

VAL3 is initialized to 0x7D which corrosponds to 100 µs. (1.25MHz clock)

 

2) PWMA Enable: Enables the PWMA.   

RUN and LDOK bits are set for the selected submodule.   

Val1 interrupt is enabled. 

 

3) PWMA ISR routine: For each of the submodules, the ISR is written which loads the new value for the high pulse. 

Disable interrupts.   

Verify that LDOK is cleared.   

Write the new value to the VAL1 register.    

Set the LDOK value.    

Enable interrupts.


4) PWMA Disable: Disables the PWMA.   

Clears the RUN bit.    

Disables the PWMA interrupts.      


While testing this PWMA module, I observed that the interrupt flags for all the VALx registers are set in the PWMA  status register except the VAL3 flag during the first iteration. After the first iteration, all the flags remain set.

Also, if the interrupt is set on VAL3 value, the ISR is not generated as the counter does not start unless the VAL1 value is written. Is this correct?  With the above code, the step pulses are generated correctly except for the first iteration, there is a small pulse of about 4 µs (low to high pulse) observed which increases as the value of VAL2 is increased (Currently kept as zero).  


Is my understanding wrong? Please help.

Find attached the excepted PWMA output timing diagram.

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