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DDR3 routing for DRAM_A[15:0] in i.MX6DQ.

Question asked by Keita Nagashima on Jan 22, 2015
Latest reply on Feb 11, 2015 by Yuri Muhin

Hello.

I have questions about DDR3 routing rule.

 

Refer to "Table 3-3. DDR3 routing by byte group" in Hardware Development Guide for i.MX6 Rev. 1.

"DRAM_A[15:0] Min : Clock (min) – 200"

 

[Q1]

Where JEDEC (or i.MX6) timing specification does this rule influence?

(Only Address output setup time? Address output hold time?)

 

[Q2]

I'd like to know the background to have decided that is "Clock (min) – 200".

 

Best Regards,

Keita

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