I have questions about DDR3 routing rule.
Refer to "Table 3-3. DDR3 routing by byte group" in Hardware Development Guide for i.MX6 Rev. 1.
"DRAM_A[15:0] Min : Clock (min) – 200"
Where JEDEC (or i.MX6) timing specification does this rule influence?
(Only Address output setup time? Address output hold time?)
I'd like to know the background to have decided that is "Clock (min) – 200".