AnsweredAssumed Answered

K60120M NAND Flash with External SRAM on flexbus, NFC, Ready/Busy RB

Question asked by pmt on Jan 9, 2015
Latest reply on Jan 15, 2015 by pmt

I'm doing a design that requires an external single NAND flash (8-bit) and SRAM (16-bit).  The NAND flash controller shares many of the same flexbus pins.  In reading some of the older posts it looks like arbitration is handled between the Flexbus and NAND Flash peripheral such that you should be able to run both.  

 

Except it looks like two pins MUST be dedicated w.r.t. the NFC:  NFC_CEx_b and NFC_RB*.  Can anyone please confirm?

 

CE needs to be dedicated because it controls the chip arbitration.  RB needs to be dedicated because it may stay actively driven even after NFC_CE goes inactive during a flash erase or program cycle (I can't imagine locking the flexbus for entire Ready/Busy cycle, which can be many milliseconds).


The big issue for me is that I am using the upper bus byte selects for my SRAM (BE23_16 and BE31_24).  This directly conflicts with RB and CE0_b lines, which are not available on any other pin.  CE1_b is available on BE15_8, which I don't use.


So my question are: 


- Can I seamlessly use NFC_CE1_b instead of NFC_CE0_b

- What is the impact of not having the RB- line available to the NFC?  Am I losing anything?  Does the NFC state machine use this line? 


I could take the RB line and simply bring it to another I/O port, and even generate an interrupt on a transition. 


Is this just an oversight of the FreeScale engineers?  Seems that RB should be able to be routed to BE7_0 as an alternate pin location.


PMT

 

Outcomes