AnsweredAssumed Answered

I have problem if SIM_CLCKDIV1[OUTDIV1] >= 3 in MK60DN512ZVLL10

Question asked by Alessio Paolucci on Jan 8, 2015
Latest reply on Jan 8, 2015 by Kerry Zhou

I try to do a driver for setting clock in MK60DN512ZVLL10.

The base structure is the same that I have done for the kl25z, and for it all well done.

Instead in MK60DN512ZVLL10 if the outdiv1 (Core clok divider) is >= of 3, the program don't work correctly.

Help me, How I can resolve this problem?

Can be a problem of this specific MCU?


Best regard

Alessio Paolucci