We want to know about i.MX6SDL IPU parallel display port.
We understand IPU parallel display port can output display data which is compliant to ITU-R BT.601 since it supports BT.656 & BT1120, is this correct?
Can i.MX6SDL IPU parallel display port output display data which is compliant to VESA DMT standard timing also?
Our concern is that whether i.MX6SDL can generate the aprepriate frequency for the pixel clock.
I understand the source clock of the pixel clock is PLL3 PFD1 as default setting.
In this case, PLL3 PFD1 is used for only display modules (IPU, EPDC, HDMI).
So I believe PLL3 PFD1 does not affect other than display modules even if the output frequency is changed and i.MX6SDL can output VESA DMT standart data.
Is this correct?