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U-Boot not completing boot sequence due to "Waiting for D_INIT timeout", any suggests on how to fix?

Question asked by Nathan Dolezal on Jan 7, 2015
Latest reply on Jan 8, 2015 by lunminliang

I recently got a OS up and running on one of the flash banks (T2080QDS Development Board), but upon a reset I noticed that the serial port was not being updated anymore.  So I switched back to the default Flash bank (setting SW6 1:4 to 0).  After doing so (and a reset) the serial port came back with the U-Boot information.  However the U-Boot boot sequence is not completing.  The boot is "hanging" after the following is displayed in the serial port "Waiting for D_INIT timeout. Memory may not work".

 

  Can someone tell me why I see this error?  Did my DDR memory go bad?  Any suggestions on how to fix this issue?

 

Here is a print out from the serial port:

U-Boot 2013.10QorIQ-SDK-T2080QDS (Apr 03 2014 - 19:13:21)

 

 

CPU0:  T2080E, Version: 1.0, (0x85380010)

Core:  e6500, Version: 2.0, (0x80400020)

Clock Configuration:

       CPU0:1533.333 MHz, CPU1:1533.333 MHz, CPU2:1533.333 MHz, CPU3:1533.333 MHz,

       CCB:600  MHz,

       DDR:1066.667 MHz (2133.333 MT/s data rate) (Asynchronous), IFC:150  MHz

       FMAN1: 700 MHz

       QMAN:  300 MHz

       PME:   600 MHz

L1:    D-cache 32 KiB enabled

       I-cache 32 KiB enabled

Reset Configuration Word (RCW):

       00000000: 12100017 15000000 00000000 00000000

       00000010: 66160002 00008400 ec027000 c1000000

       00000020: 00000000 00000000 00000000 000307fc

       00000030: 00000000 00000000 00000000 00000004

Board: T2080QDS, Sys ID: 0x28, Board Arch: V1, Board Version: A, boot from vBank0

FPGA: v11 (T1040QDS_2014_0318_1724), build 317 on Tue Mar 18 21:24:26 2014

SERDES Reference Clocks:

SD1_CLK1=156.25MHZ, SD1_CLK2=100.00MHz

SD2_CLK1=100.00MHz, SD2_CLK2=100.00MHz

I2C:   ready

SPI:   ready

DRAM:  Initializing....using SPD

Detected UDIMM 9JSF25672AZ-2G1K1

Waiting for D_INIT timeout. Memory may not work.

    DDR:

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