We have some questions about DVFS.
Would you teach about the following contents?
The following contents are explained in section 10.4.1.4.1 Power distribution of the reference manual.
10.4.1.4.1 Power distribution (P.524)
"Cortex-A9 Core Platform - DVFS and power gating."
Does this mean LDO_DIG(ARM) of "Figure 10-6. i.MX 6Solo/6DualLite Power Tree"(P.518)?
I understand that DVFS controls the voltage by using PMU_MISC2n register.
Does DVFS control LDO_DIG(SoC) and LDO_DIG(PU)?
Or Does DVFS control only LDO_DIG(ARM)?