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About voltage control of DVFS for i.MX6Solo

Question asked by yuuki on Jan 6, 2015
Latest reply on Jan 12, 2015 by yuuki

Dear all,

 

We have some questions about DVFS.
Would you teach about the following contents?

 

Q1)
The following contents are explained in section 10.4.1.4.1 Power distribution of the reference manual.

10.4.1.4.1 Power distribution (P.524)
"Cortex-A9 Core Platform - DVFS and power gating."

 

Does this mean LDO_DIG(ARM) of "Figure 10-6. i.MX 6Solo/6DualLite Power Tree"(P.518)?

 

Q2)
I understand that DVFS controls the voltage by using PMU_MISC2n register.

Does DVFS control LDO_DIG(SoC) and LDO_DIG(PU)?
Or Does DVFS control only LDO_DIG(ARM)?

 

Best Regards,
Yuuki

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