Dear Sir or Madam,
I have a question about the layout of DDR3 in i.MX6Q SABRE-AI.
SABRE-AI is designed by four DDR3 with T-topology opposite sides.
But, as a result of the simulation of the customer, as for the both side implementing of BGA, the danger of solder crack is high with the heat stress to DDR solder ball.
Please give me your comment or advice.
How did freescale review to fix the layout?
Is there a problem to the reliability?