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IMX257 communicate with FPGA by WEIM

Question asked by 志明 李 on Dec 29, 2014
Latest reply on Dec 30, 2014 by igorpadykov

Hi, everyone!

    Now I‘m using imx 257 core board (OS for LINUX) of WEIM (external memory interface) 16 data synchronization (address 14), FPGA like an external memory to read and write, I used CS1 chip  connected with FPGA the election, as the configuration of the drive:

 

mxc_request_iomux(MX25_PIN_A10, MUX_CONFIG_FUNC);
mxc_request_iomux(MX25_PIN_A13, MUX_CONFIG_FUNC);

 

 

mxc_request_iomux(MX25_PIN_D0,  MUX_CONFIG_FUNC);
mxc_request_iomux(MX25_PIN_D1,  MUX_CONFIG_FUNC);
mxc_request_iomux(MX25_PIN_D2,  MUX_CONFIG_FUNC);
mxc_request_iomux(MX25_PIN_D3,  MUX_CONFIG_FUNC);
mxc_request_iomux(MX25_PIN_D4,  MUX_CONFIG_FUNC);
mxc_request_iomux(MX25_PIN_D5,  MUX_CONFIG_FUNC);
mxc_request_iomux(MX25_PIN_D6,  MUX_CONFIG_FUNC);
mxc_request_iomux(MX25_PIN_D7,  MUX_CONFIG_FUNC);
mxc_request_iomux(MX25_PIN_D8,  MUX_CONFIG_FUNC);
mxc_request_iomux(MX25_PIN_D9,  MUX_CONFIG_FUNC);
mxc_request_iomux(MX25_PIN_D10, MUX_CONFIG_FUNC);
mxc_request_iomux(MX25_PIN_D11, MUX_CONFIG_FUNC);
mxc_request_iomux(MX25_PIN_D12, MUX_CONFIG_FUNC);
mxc_request_iomux(MX25_PIN_D13, MUX_CONFIG_FUNC);
mxc_request_iomux(MX25_PIN_D14, MUX_CONFIG_FUNC);
mxc_request_iomux(MX25_PIN_D15, MUX_CONFIG_FUNC);

 

 

mxc_request_iomux(MX25_PIN_EB0, MUX_CONFIG_FUNC);
mxc_request_iomux(MX25_PIN_EB1, MUX_CONFIG_FUNC);
mxc_request_iomux(MX25_PIN_OE,  MUX_CONFIG_FUNC);
mxc_request_iomux(MX25_PIN_CS1, MUX_CONFIG_FUNC);
mxc_request_iomux(MX25_PIN_RW,  MUX_CONFIG_FUNC);

 

 

//mxc_iomux_set_pad(MX25_PIN_A10, PAD_CTL_DRV_HIGH|PAD_CTL_PUE_KEEPER );
mxc_iomux_set_pad(MX25_PIN_A13, PAD_CTL_DRV_HIGH|PAD_CTL_PUE_KEEPER );
mxc_iomux_set_pad(MX25_PIN_D0,  PAD_CTL_HYS_CMOS|PAD_CTL_DRV_HIGH|PAD_CTL_PKE_ENABLE|PAD_CTL_100K_PU|PAD_CTL_ODE_CMOS|PAD_CTL_DRV_3_3V|PAD_CTL_PUE_KEEPER|PAD_CTL_SRE_FAST);
mxc_iomux_set_pad(MX25_PIN_D1,  PAD_CTL_HYS_CMOS|PAD_CTL_DRV_HIGH|PAD_CTL_PKE_ENABLE|PAD_CTL_100K_PU|PAD_CTL_ODE_CMOS|PAD_CTL_DRV_3_3V|PAD_CTL_PUE_KEEPER|PAD_CTL_SRE_FAST);
mxc_iomux_set_pad(MX25_PIN_D2,  PAD_CTL_HYS_CMOS|PAD_CTL_DRV_HIGH|PAD_CTL_PKE_ENABLE|PAD_CTL_100K_PU|PAD_CTL_ODE_CMOS|PAD_CTL_DRV_3_3V|PAD_CTL_PUE_KEEPER|PAD_CTL_SRE_FAST);
mxc_iomux_set_pad(MX25_PIN_D3,  PAD_CTL_HYS_CMOS|PAD_CTL_DRV_HIGH|PAD_CTL_PKE_ENABLE|PAD_CTL_100K_PU|PAD_CTL_ODE_CMOS|PAD_CTL_DRV_3_3V|PAD_CTL_PUE_KEEPER|PAD_CTL_SRE_FAST);
mxc_iomux_set_pad(MX25_PIN_D4,  PAD_CTL_HYS_CMOS|PAD_CTL_DRV_HIGH|PAD_CTL_PKE_ENABLE|PAD_CTL_100K_PU|PAD_CTL_ODE_CMOS|PAD_CTL_DRV_3_3V|PAD_CTL_PUE_KEEPER|PAD_CTL_SRE_FAST);
mxc_iomux_set_pad(MX25_PIN_D5,  PAD_CTL_HYS_CMOS|PAD_CTL_DRV_HIGH|PAD_CTL_PKE_ENABLE|PAD_CTL_100K_PU|PAD_CTL_ODE_CMOS|PAD_CTL_DRV_3_3V|PAD_CTL_PUE_KEEPER|PAD_CTL_SRE_FAST);
mxc_iomux_set_pad(MX25_PIN_D6,  PAD_CTL_HYS_CMOS|PAD_CTL_DRV_HIGH|PAD_CTL_PKE_ENABLE|PAD_CTL_100K_PU|PAD_CTL_ODE_CMOS|PAD_CTL_DRV_3_3V|PAD_CTL_PUE_KEEPER|PAD_CTL_SRE_FAST);
mxc_iomux_set_pad(MX25_PIN_D7,  PAD_CTL_HYS_CMOS|PAD_CTL_DRV_HIGH|PAD_CTL_PKE_ENABLE|PAD_CTL_100K_PU|PAD_CTL_ODE_CMOS|PAD_CTL_DRV_3_3V|PAD_CTL_PUE_KEEPER|PAD_CTL_SRE_FAST);
mxc_iomux_set_pad(MX25_PIN_D8,  PAD_CTL_HYS_CMOS|PAD_CTL_DRV_HIGH|PAD_CTL_PKE_ENABLE|PAD_CTL_100K_PU|PAD_CTL_ODE_CMOS|PAD_CTL_DRV_3_3V|PAD_CTL_PUE_KEEPER|PAD_CTL_SRE_FAST);
mxc_iomux_set_pad(MX25_PIN_D9,  PAD_CTL_HYS_CMOS|PAD_CTL_DRV_HIGH|PAD_CTL_PKE_ENABLE|PAD_CTL_100K_PU|PAD_CTL_ODE_CMOS|PAD_CTL_DRV_3_3V|PAD_CTL_PUE_KEEPER|PAD_CTL_SRE_FAST);
mxc_iomux_set_pad(MX25_PIN_D10, PAD_CTL_HYS_CMOS|PAD_CTL_DRV_HIGH|PAD_CTL_PKE_ENABLE|PAD_CTL_100K_PU|PAD_CTL_ODE_CMOS|PAD_CTL_DRV_3_3V|PAD_CTL_PUE_KEEPER|PAD_CTL_SRE_FAST);
mxc_iomux_set_pad(MX25_PIN_D11, PAD_CTL_HYS_CMOS|PAD_CTL_DRV_HIGH|PAD_CTL_PKE_ENABLE|PAD_CTL_100K_PU|PAD_CTL_ODE_CMOS|PAD_CTL_DRV_3_3V|PAD_CTL_PUE_KEEPER|PAD_CTL_SRE_FAST);
mxc_iomux_set_pad(MX25_PIN_D12, PAD_CTL_HYS_CMOS|PAD_CTL_DRV_HIGH|PAD_CTL_PKE_ENABLE|PAD_CTL_100K_PU|PAD_CTL_ODE_CMOS|PAD_CTL_DRV_3_3V|PAD_CTL_PUE_KEEPER|PAD_CTL_SRE_FAST);
mxc_iomux_set_pad(MX25_PIN_D13, PAD_CTL_HYS_CMOS|PAD_CTL_DRV_HIGH|PAD_CTL_PKE_ENABLE|PAD_CTL_100K_PU|PAD_CTL_ODE_CMOS|PAD_CTL_DRV_3_3V|PAD_CTL_PUE_KEEPER|PAD_CTL_SRE_FAST);
mxc_iomux_set_pad(MX25_PIN_D14, PAD_CTL_HYS_CMOS|PAD_CTL_DRV_HIGH|PAD_CTL_PKE_ENABLE|PAD_CTL_100K_PU|PAD_CTL_ODE_CMOS|PAD_CTL_DRV_3_3V|PAD_CTL_PUE_KEEPER|PAD_CTL_SRE_FAST);
mxc_iomux_set_pad(MX25_PIN_D15, PAD_CTL_HYS_CMOS|PAD_CTL_DRV_HIGH|PAD_CTL_PKE_ENABLE|PAD_CTL_100K_PU|PAD_CTL_ODE_CMOS|PAD_CTL_DRV_3_3V|PAD_CTL_PUE_KEEPER|PAD_CTL_SRE_FAST);

 

 

mxc_iomux_set_pad(MX25_PIN_EB0, PAD_CTL_DRV_HIGH|PAD_CTL_PUE_PULL);
mxc_iomux_set_pad(MX25_PIN_EB1, PAD_CTL_DRV_HIGH|PAD_CTL_PUE_PULL);
mxc_iomux_set_pad(MX25_PIN_OE,  PAD_CTL_DRV_HIGH|PAD_CTL_PUE_PULL);
//
mxc_iomux_set_pad(MX25_PIN_RW,  PAD_CTL_DRV_HIGH|PAD_CTL_PUE_PULL);

 

 

//mxc_iomux_set_pad(MX25_PIN_CTL_GRP_DDRTYPE,0x0 << 11);//DDR_TYPE = 00 i don't know how to set the DDRTPYE

// mxc_iomux_set_input(iomux_input_select_t input,u32 config)

 

//VA_ADDR = 0xFC522000

writel( 0x00001E00, VA_ADDR + 0x10);//CSCR1U
writel( 0xA0050841, VA_ADDR + 0x14);//CSCR1L
writel( 0x00005000, VA_ADDR + 0x18);//CSCR1A

 

 

volatile unsigned long *eim_mem = NULL;
eim_mem = (unsigned long*)ioremap(WEIM_CS1_BASE_ADDR, 0x4000);
// WEIM_CS1_BASE_ADDR 0xA8000000
if(!eim_mem)
{
    printk("Failed to remap eim_mem\n");

}

//write many times

writew( 0x55aa, eim_mem);

 

 

 

and there is no data on the CS1,anyone can help me?

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