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i.MX6: is there an option for gen-lock at IPU video output?

Question asked by Sharon Golan on Dec 26, 2014
Latest reply on Dec 27, 2014 by igorpadykov

Hi.

 

We are using the LVDS to output SD/HD video from the SoC. Due to constraints in the display side, I would like to check if the IPU can be configured to output video according to both pixel-clock and Vsync from external source (i.e. gen-lock) .

 

Does the i.MX6 support video output per Vsync from external source ? if positive, I'll appreceiate any guidance regarding the steps needed to set such a configuration.


Thank you.

sharon



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