AnsweredAssumed Answered

ls1021a WDOG1 is not working

Question asked by nix yeah on Dec 24, 2014
Latest reply on Jan 6, 2015 by lunminliang

The WDOG1 on twr-ls1021a X4(SCH Rev C1) board seems not working. Setting timeout and enable the wdog1 will not cause a wdog reset.

 

Is it because of it using "All WDOG modules use 32 KHz clock, driven at device input RTC or LP_RTC pin for their counters", and the SCH shows that the "GPIO1_14/RTC" and "TA_BB_RTC" are not used at all? So the WDOG1 time counters does not work at all?

 

Below are my test log, and it shows that the same steps will make i.MX6DL WDOG1 work while twr-ls1021a fail.

-------------------------------------------------------------------------------------------------------------------------------------------------------------

Test log on a i.MX6DL Sabre Auto board

a. normal reset (by push reset button)

=>  md.w 20bc000 4

020bc000: 0030 0000 0010 0004                0....... //Power On Reset

b. SRS bit of WCR

=> mm.w 20bc000

020bc000: 0030 ? 0020

020bc

U-Boot 2014.07 (Jul 16 2014 - 14:07:21)

=> md.w 20bc000 4

020bc000: 0030 0000 0001 0004                0....... //software reset

c. watchdog enable for 10 seconds timeout

=> mm.w 20bc000

020bc000: 0030 ? 1334

020bc002: 0000 ? .

=>

U-Boot 2014.07 (Jul 16 2014 - 14:07:21)

CPU:   Freescale i.MX6DL rev1.1 at 792 MHz

Reset cause: WDOG

=> md.w 20bc000 4

020bc000: 0030 0000 0002 0004                0....... //watchdog timeout

 

So the WDOG function on this board is OK.

------------------------------------------------------------------------------------------------------------------------------------------------------------------------

Test on a TWR-LS1021A X4 board (SCH RevC1)

 

big endian wdog:

a. normal reset by push reset button

=> md.w 2ad0000 4

02ad0000: 3000 0000 1000 0400                .0...... //manual reserved bit of WRSR[4]

b. soft reset by SRS of WCR(works)

=> mm.w 2ad0000

02ad0000: 3000 ? 2000ÿ

U-Boot 2014.01Layerscape-SDK-V1.0+g79ab344 (Jun 25 2014 - 14:16:47)

=>  md.w 2ad0000 4

02ad0000: 3000 0000 1000 0400                .0...... // no bit indicating of WRSR[0]

c. watchdog timeout reset for 10 seconds

=> mm.w 2ad0000

02ad0000: 3000 ? 3413

02ad0002: 0000 ? .

=> md.w 2ad0000 4

02ad0000: 3413 0000 1000 0400                .4...... // cannot reset at all

No reset after even 20 seconds

So the WDOG1 is not functional on this board.

 

---------------------------------------------------------------------------------------------------------------------------------------------

Also, I found that below:

Appendix Endianess says DCFG is big endian, but it seems that these are little endian.

Is my guess wrong?

 

DCFG_CCSR_RSTRQMR1:

22 - CORE_WDOG_RST_MSK

Core watchdog reset request mask.

0 Core watchdog reset request can cause a reset request

1 Core watchdog reset request cannot cause a reset request

=> md 1ee00c0

01ee00c0: 00400000 00000000 00400000 00000000    ..@.......@.....

=> mm 1ee00c0

01ee00c0: 00400000 ? 00000000                   // Caused a immediate reset, why?

U-Boot 2014.01Layerscape-SDK-V1.0+g79ab344 (Jun 25 2014 - 14:16:47)

Outcomes