In MPC5644A datasheet Rev 7, §3.17.8 "DSPI timing" mentions that the "Data Hold Time for Inputs" (10) is -4 ns and the "Data Hold Time for Outputs" (12) is -7.5 ns (VDDEH=3 –3.6 V). I am using CPOL=0 and CPHA=1 so I look at "Figure 24. DSPI classic SPI timing — master, CPHA = 1". What does the negative number mean?
a) The MPC5644A will keep the SOUT valid for 7,5 ns after the rising clock edge
b) The MPC5644A will keep the SOUT valid up to 7,5 ns before the rising clock edge
Indeed, the figure is showing a period which is at the right of the clock's edge... Same question for inputs (10).