I am using T2080 processor in my design. In this planned to interface a following MT41K1G8TRF-125 IT E micron memory to the processor DDR3L interface. The above micron part has dual die & a total memory of 8Gbit(4Gbit+4Gbit), each chip has 8bit data width. I am planning to interface 8devices to the processor to meet the 64bit interface plus one additional chip for the ECC. But the selected memory chip has single clock pin dual ODT pins,two clock enable pins & two chip select pins for each indugel die. In this case I have connected clock-0 to all 9 devices. chip select 0&1 is connected to all 9 devices. clock enable 0&1 is connected to all 9 devices. In this I need following clarification: For chip select-1 & clock enable-1 whether the clock-0 is active irrespective chip select ?