I am considering pin migration between 50MHz and 120MHz K21 devices in the 121-MAPBGA packages. It appears the 120MHz device pinout is a superset in many ways so shared features should be available with a single board design. There are a couple of questions though:
(1) K21_120 includes an extra VDD/VSS pair in the 121-MAPBGA package. These are NC pins on the K21_50 device. How should I design a board to accommodate both devices? Can the NC pins be connected to VDD/VSS for the 50MHz device?
(2) Are there any considerations for clocking to support both devices? I realize FEI (FLL-Enabled Internal) mode won't accommodate 120MHz operation, so I believe I should populate an external crystal. Is there any preference for frequency?