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Pad Control register (IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK) Problem

Question asked by David Niebauer on Dec 22, 2014
Latest reply on Jan 4, 2016 by Andrew Dyer



I got a running System over EIM Bus Interface for the i.mx6dl in synchronous mode. I got a problem regarding to

i.MX 6Solo/6DualLite Applications Processor Reference Manual, Rev. 0, 11/2012

37.3.318 Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK).


If i am changing the DSE register (Drive strength field) to a value bigger than 60_OHM,

i can see that the i.MX6dl captures the Input Data one cycle too early!!!!

It seems that only the DSE setting on the eim_bclk port is responsible for the early data sample,

if i change the DSE values for other eim specific ports, i can't notice any problems for the bus communication!


I took a look at the oscilloscope and i haven't seen any timing specific differences of the peripherals for the eim signals between and different xx_ohm values =>

the problem must be generated from the i.MX6dl!


According to 22.8.3 Chip Select n Read Configuration Register 1 (EIM_CSnRCR1),

i need to set the RWSC register +1 that i will get correct read data if i set the eim_bclk port to a value > 60_ohm!


Does someone has an explaination for this behaviour?