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DDR4 write-leveling capabilities

Question asked by Benjamin Fox on Dec 18, 2014
Latest reply on Dec 22, 2014 by lunminliang

How much Clock-Strobe skew can the DDR4 capable T1024 Processors compensate for during write-leveling? A general PCB guideline is to wire the clock as long the strobe, however can the QorIQ DDR4 controllers maintain tDQSS requirements if the clock is shorter than the corresponding strobes and by how much?

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