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CSI1 and CSI0 with MX6S

Question asked by Martin Bachmann on Dec 15, 2014
Latest reply on May 14, 2015 by Vladislav Kalutskiy

Is it possible to synchronously receive on both parallel camera inputs (CSI0 and CSI1) with i.MX6 Single Core?

We like to develop a custom board with two Aptina MT9V034. Each are connected to a CSI parallel port of a MX6 single core. The cameras are triggered at the same time. The data should then be written to the DDR memory (no processing in IPU). Is that possible with the single core? I found no restrictions in the reference manual.