Our partner found a problem about i.MX6S CCM with L3.0.35_4.1.0 BSP.
Actually, they are using CLKO2 to audio master clock.
Then, they changed CLKO2_DIV setting every 10 seconds when they executed laod test.
In this case, rarely CLKO2 does not output clock after changing the divider setting.
The frequency of this problem is once for several tens of thousand times. (There is variation)
Would you let me know the mechanism why the CLKO2_DIV does not work well rarely?
Would you let me know a procedure to avoid this problem?
(e.g. stop clock source when change CLKO2_DIV setting.)