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iMX6 Solo SPI: XCH behaviour in master mode.

Question asked by Mark Siggins on Dec 10, 2014
Latest reply on Apr 21, 2015 by Yuri Muhin


I am seeing the XCH bit in the CONREG register being cleared while the spi transfer is still in progress, when the reference manual states in 21.7.4 that:


"The XCH bit remains set while either the data exchange is in progress, or when the ECSPI is waiting for an active input if SPIRDY is enabled through DRCTL. This bit is cleared automatically when all data in the TXFIFO and the shift register has been shifted out".


I am seeing this erroneous behaviour when I set the EN bit to '0', after seeing XCH=0 suggesting the transfer is finished, to save having to manually flush the RX fifo after a write transaction. I can see this even at slow speeds, SPI clock is about 2MHz, and short messages, even a single byte. With careful timing of the single byte write, it is even possible to see a partial byte being transferred, 1,2 or 3 clocks, instead of 8. This suggests that the XCH bit does NOT wait for the TX shift register to empty, it goes low as soon as the TXFIFO is empty. Alternatively, setting EN low even earlier, can cause a complete lack of SPI activity, even though XCH indicates that the transfer has completed.


Can someone at Freescale confirm this behaviour?


And how does the behaviour of the TC bit in STATREG differ, if at all? i.e. can the TC bit be used to detect that the transfer really is over?


For short write messages, (and any read messages), we can be bullet-proof by waiting on words appearing in the RXFIFO, as they simply won't be there if the bits haven't been shifted in. But for long write messages, (writing to a page of flash memory for example), it'll be a pain to have to read the exact amount of garbage data, just to be certain that the transfer has actually finished. We need either XCH or TC to work properly - and XCH doesn't seem to.


Cheers for now,