i.MX6SDL EIM synchronous access when BL=Continuous burst length.

[satoshishimoda]

Hi community,

Our partner have some questiosn about i.MX6SDL EIM.

They understand the EIM access will be burst when BL=Continuous burst length and APR=0 (synchronous access).

Then, please see their questions as following.

[Q1]

The finish timing of burst access is handled by i.MX6 EIM if WFL=1 and RFL=1.

Is this correct?

[Q2]

With the condition of Q1, software can execute a fix length access (e.g. single access).

Is this correct?

[Q3]

The finish timing of burst access is handled by EIM slave if WFL=1 and RFL=1.

Is this correct?

[Q4]

With the condition of Q2, EIM slave finishes a access by WAIT signal.

Is this correct?

Best Regards,

Satoshi Shimoda

[igorpadykov · Accepted solution]

Hi Satoshi

RFL,WFL do not have relation to burst behaviour.

RFL,WFL=0 means that supported WAIT signal, it is

checked after RWSC/ WWSC cycles.

RFL,WFL=1 means that WAIT signal is ignored , burst (if any,

may be just one access, that is single beat in burst)

starts after RWSC/ WWSC cycles.

IMX6SDLRM Figure 22-12 shows such waveforms

IMX6DQRM p.1047 Figure 22-12 gives example of "burst length =4" -correspond

to RD0,1,2,3 and "number of skipped BCLK =3" :   2 - WAIT and one due to RWSC=1.

Best regards

igor

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