Is there any approach available (like uboot configuration parameter, etc..) to disable level 2 and level 3 caches on e500mc platform ?
I can think of L2E bit of L2CSR0 register, but looking for something as in part of boot time itself .. In parallel, searching surfing for the code (linux) where these caches are booted (init sequence) and also not sure how safe it is to comment (remove) those cache init/powerup code.
And also, if we disable the L2 cache using L2E bit (-> 0), is there any alternative method available to verify the status of L2 cache(on/off) other than checking this bit status ?
Thanks in Advance.