I found the power-up sequence restrictions in 4.2.1 Power-Up Sequence of IMX6SDLIEC.pdf.
My customer not use external SRC_POR_B signal(left unconnected) and also not use PMIC design. Other design is refer to SPF-27516_C3.pdf(Sabre_sdb Schematics).
Their design's power-up sequence is also not same with SPF-27516_C3.pdf(Sabre_sdb Schematics).
1)Customer's 1.425V supply(VDD_SOC/VDD_ARM_IN) power up after the DDR3 supply(the sequence is not the same with the Sabre_sdb supply sequence).
2)In Sabre_sdb supply sequence, DDR_VREF power up in the same sequence with DDR_1.5V. But in customer's design, VREFDDR0.75V power up before DDR3 1.5V supply(more than 14.5ms).
I don't know whether the sequence is OK as I can not find any restrictions information for the case.
Thank you for your help and look forward to your kindly answer.