AnsweredAssumed Answered

i.MX6DL DDR register setting value by .inc file in DDR stress tester.

Question asked by Satoshi Shimoda on Dec 5, 2014
Latest reply on Dec 15, 2014 by igorpadykov

Hi community,

 

We have two questions about DDR Stress Test in https://community.freescale.com/docs/DOC-96412#.

I think it is better to post this question in https://community.freescale.com/docs/DOC-96412#, but I could not post a comment.

Anyway, please see our questions as following.

 

[Q1]

Please see IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET setting value in MX6DL_SabreSD_DDR3_register_programming_aid_v1.5.inc.

It is "setmem /32 0x020e0494 = 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET".

Next, please see chapter 37.4.289 (IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET) in IMX6SDLRM (Rev.1).

According to the setting value in the .inc file, DDR_SEL is set to "RESERVED0", not "DDR3".

Is this no problem?

If it is no problem, would you let me know why it is set to "RESERVED0"?

 

 

[Q2]

Please see IOMUXC_SW_PAD_CTL_GRP_DDRMODE setting value in MX6DL_SabreSD_DDR3_register_programming_aid_v1.5.inc.

It is "setmem /32 0x020e0760 = 0x00020000 // IOMUXC_SW_PAD_CTL_GRP_DDRMODE".

Next, please see chapter 37.4.464 (IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL) in IMX6SDLRM (Rev.1).

According to the setting value in the .inc file, DDR_INPUT is set to "DIFFERENTIAL" even though DRAM_DATAxx signals are not differential.

Is it no problem?

If it is no problem, would you let me know why it is set to "DIFFERENTIAL?

 

 

Best Regards,

Satoshi Shimoda

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