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how to set ENET_CLK to 25MHz ?

Question asked by Zhao Wei on Dec 4, 2014
Latest reply on Dec 5, 2014 by Zhao Wei

From the following picture( capture from MCIMX28RM.pdf  --- 10.2.2 Logical Diagram of Clock Domains [Page 885] )

i want to enet_clk output 25MHz instead of 50MHz,how to set register by ENET Controller? i cannot find any register to describe how to divide the ref_enet_pll ?