Minimum SPI Delay after Transfer on MPC5644A

[EAlepins]

Hi,

In MPC5644A DSPI module, CTARn[PDT and DT] can be configured to set a delay inserted between chip select negation and next chip select assertion. As opposed to other timing configurations, the datasheet does not impose any minimum on this value. Can I then assume the smallest that it's possible to configure in the registers will be ok for the MCU? (i.e. PDT=00 and DT=00, which yields a delay of 1 * 2 * 1/fsys)

Thanks.

[lukaszadrapa]

Hi,

yes, it is OK for the MCU. It depends rather on slave if it is able to accept such short delay between the chip select assertion.

Regards,

Lukas