Dear Sir or Madam,
Refer to Table 3-5. Total signal etch (DDR3) in Hardware Development Guide for i.MX6DQ6SDL, Rev. 1.
There is description of DRAM_SDCLK0 : 2120.044[Mils].
My customer measured the DRAM_SDCLK0 length on i.MX6Q SABRE-AI.
Actualｌy the DRAM_SDCLK0 length looked 1849.483[Mils].
Refer to attached file: "DDR3_SDCLK_Length.xlsx"
Should we think including the branch wiring about each signal length?
Or, can we ignore the branch wiring length?