The Reference Manual for the MC56F847xx family states that PWMB has the registers: PWMB_SMnFRACVALx and the PWMB_SMnFRCTRL (pages 744-751).
They were included in the last revision as stated on page 1097 (A.28 PWMB changes).
The processor header file (...\CW MCU v10.6\MCU\lib\wizard_data\DSC\DataBase\derivatives\include\MC56F84789_rev1.0.h), however, do not include them, and it has to be done by hand.
Does the processor really have the fractional registers for PWMB?
page 1097 (A.28 PWMB changes) also states that:
"In Introduction section, reworded to clearly indicate that PWMB supports digital dithering, while PWMA does not
support digital dithering."
However, in page 743, the introduction says the opposite:
The primary difference between PWMB and PWMA: PWMA supports NanoEdge placement (digital dithering); PWMB does not support NanoEdge placement (digital dithering).
I suppose that page 743 is correct, as the rest of the document support its version. Am I correct?
Thanks for the attention.