AnsweredAssumed Answered

i.MX6 V4L2 enqueue and dequeue timing.

Question asked by Satoshi Shimoda on Nov 26, 2014
Latest reply on Dec 2, 2014 by Bio_TICFSL

Hi community,


Our partner have a question about i.MX6S V4L2 driver of L3.0.35_4.1.0 BSP.


They understand the timing that V4L2 driver receive data as following.


A buffer which is enqueued to driver by VIDIOC_QBUF have two status.


And it will be able to be dequeued (be able to write a next data to input buffer which was enqueued in previous step) when V4L2_BUF_FLAG_DONE sutatus.



However, according to the source code (comment around line 743 in drivers/media/video/mxc/output/mxc_vout.c), the first buffer can be dequeued after 3 buffers is enqueued if input buffer size = output buffer size.

In this case, can our partner check whether the next data can be written to the first buffer before the 3rd buffer is enqueued?



Best Regards,

Satoshi Shimoda