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About the SEQ_CLK_SPEED field of PF0100

Question asked by yuuki on Nov 26, 2014
Latest reply on Nov 27, 2014 by Artur Petukhov

Dear All,

 

There is description about SEQ_CLK_SPEED field of OTP PU CONFIG register in Start-up Sequence.

 

However, there is OTP PU CONFIG register from OTP PU CONFIG1 to OTP PU CONFIG3.
And, there is SEQ_CLK_SPEED[1:0] from SEQ_CLK_SPEED1[1:0] to SEQ_CLK_SPEED3[1:0].

 

Would you teach the reason that these 3 registers are here?
How should we use these registers?

 

http://cache.freescale.com/files/analog/doc/data_sheet/MMPF0100.pdf
- Table 12. Start-up Sequence (P.24)
- Table 13. Start-up Sequence Clock Speed (P.24)
- Table 137. Extended Page 1 (continued) (P.129)

 

Best Regards,
Yuuki

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