AnsweredAssumed Answered

iMX6 DDR3 Stress Test calibration tool  problems

Question asked by Otto Blom on Nov 24, 2014
Latest reply on Nov 24, 2014 by Yuri Muhin

Hello There,

 

We have a custom board very similar to the imx6q SabreSD reference design. DDR3 components and schematic are identical, but layout is somewhat different in that we have all 4 chips on the top of the board. The board boots up and runs using the SabreSD DDR calibration values provided in the Yocto U-boot & Kernel, but we are seeing some instability problems so we tried running the DDR3 Stress Tester 1.0.3. Using the MX6Q_SabreSD_DDR3_register_programming_aid_v1.5.inc file we are not able to run the write leveling successfully. It comes back with values, but the subsequent DQS Gating calibration and DDR stress test fails. However, if the write leveling calibration is skipped the DQS gating calibration and the stress test runs OK (528Mhz). I tried setting different values for WALAT as suggested elsewhere on the forum, but with the same outcome. See logs below

 

I'm not sure what this means or what to do at this points, so any help is appreciated

 

Thanks,

 

/Otto

 

-----------------------------------

//WALAT Settings

setmem /32      0x021b0018 =    0x00001740    // MMDC0_MDMISC  //0x40001740  WALAT 0

//setmem /32    0x021b0018 =    0x00011740    // MMDC0_MDMISC  //0x40001740  WALAT 1

//setmem /32    0x021b0018 =    0x00021740    // MMDC0_MDMISC  //0x40001740  WALAT 2

//setmem /32    0x021b0018 =    0x00031740    // MMDC0_MDMISC  //0x40001740  WALAT 3

---------------------------------------

 

 

 

--------------------------------------------------------

Stress-test running Write Level calibration

******************************

    DDR Stress Test (1.0.3) for MX6DQ

    Build: Jun 25 2014, 12:09:21

    Freescale Semiconductor, Inc.

******************************

=======DDR configuration==========

BOOT_CFG3[5-4]: 0x00, Single DDR channel.

DDR type is DDR3

Data width: 64, bank num: 8

Row size: 14, col size: 10

Chip select CSD0 is used

Density per chip select: 1024MB

==================================

What ARM core speed would you like to run?

Type 0 for 650MHz, 1 for 800MHz, 2 for 1GHz, 3 for 1.2GHz

  ARM set to 1.2GHz


Please select the DDR density per chip select (in bytes) on the board

Type 0 for 2GB; 1 for 1GB; 2 for 512MB; 3 for 256MB; 4 for 128MB; 5 for 64MB; 6 for

For maximum supported density (4GB), we can only access up to 3.75GB.  Type 9 to se

  DDR density selected (MB): 1024

 

Calibration will run at DDR frequency 528MHz. Type 'y' to continue.

If you want to run at other DDR frequency. Type 'n'

  DDR Freq: 528 MHz


Would you like to run the write leveling calibration? (y/n)

  Please enter the MR1 value on the initilization script

  This will be re-programmed into MR1 after write leveling calibration

  Enter as a 4-digit HEX value, example 0004, then hit enter

0004 You have entered: 0x0004


Start write leveling calibration

Write leveling calibration completed

MMDC_MPWLDECTRL0 ch0 after write level cal: 0x017F017F

MMDC_MPWLDECTRL1 ch0 after write level cal: 0x0004017B

MMDC_MPWLDECTRL0 ch1 after write level cal: 0x017F0013

MMDC_MPWLDECTRL1 ch1 after write level cal: 0x017F000A

 

Would you like to run the DQS gating, read/write delay calibration? (y/n)

Starting DQS gating calibration...

. . . . . . . . . . . . . . ERROR FOUND, we can't get suitable value !!!!

dram test fails for all values.

 

The DDR stress test can run with an incrementing frequency or at a static freq

To run at a static freq, simply set the start freq and end freq to the same value

Would you like to run the DDR Stress Test (y/n)?

 

Enter desired START freq (135 to 672 MHz), then hit enter.

Note: DDR3 minimum is ~333MHz, do not recommend to go too much below this.

500

  The freq you entered was: 500

 

Enter desired END freq (135 to 672 MHz), then hit enter.

Make sure this is equal to or greater than start freq

600

  The freq you entered was: 600

 

Beginning stress test

 

loop: 1

DDR Freq: 500 MHz

t0.1: data is addr test

Address of failure: 0x10000000

Data was: 0x00aa00aa

But pattern  should match address

--------------------------------------------------------

 

 

Stress test running DQS Calibration & DDR Stress test

--------------------------------------------------------

******************************

    DDR Stress Test (1.0.3) for MX6DQ

    Build: Jun 25 2014, 12:09:21

    Freescale Semiconductor, Inc.

******************************

=======DDR configuration==========

BOOT_CFG3[5-4]: 0x00, Single DDR channel.

DDR type is DDR3

Data width: 64, bank num: 8

Row size: 14, col size: 10

Chip select CSD0 is used

Density per chip select: 1024MB

==================================

What ARM core speed would you like to run?

Type 0 for 650MHz, 1 for 800MHz, 2 for 1GHz, 3 for 1.2GHz

  ARM set to 1.2GHz


Please select the DDR density per chip select (in bytes) on the board

Type 0 for 2GB; 1 for 1GB; 2 for 512MB; 3 for 256MB; 4 for 128MB; 5 for 64MB; 6 for

For maximum supported density (4GB), we can only access up to 3.75GB.  Type 9 to se

  DDR density selected (MB): 1024


Calibration will run at DDR frequency 528MHz. Type 'y' to continue.

If you want to run at other DDR frequency. Type 'n'

  DDR Freq: 528 MHz


Would you like to run the write leveling calibration? (y/n)

  You have chosen not to run the write level calibration


Would you like to run the DQS gating, read/write delay calibration? (y/n)

Starting DQS gating calibration...

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . .

BYTE 0:

        Start:          HC=0x01 ABS=0x00

        End:            HC=0x04 ABS=0x48

        Mean:            HC=0x02 ABS=0x63

        End-0.5*tCK:    HC=0x03 ABS=0x48

        Final:          HC=0x03 ABS=0x48

BYTE 1:

        Start:          HC=0x01 ABS=0x64

        End:            HC=0x04 ABS=0x3C

        Mean:            HC=0x03 ABS=0x10

        End-0.5*tCK:    HC=0x03 ABS=0x3C

        Final:          HC=0x03 ABS=0x3C

BYTE 2:

        Start:          HC=0x00 ABS=0x70

        End:            HC=0x04 ABS=0x28

        Mean:            HC=0x02 ABS=0x4C

        End-0.5*tCK:    HC=0x03 ABS=0x28

        Final:          HC=0x03 ABS=0x28

BYTE 3:

        Start:          HC=0x01 ABS=0x54

        End:            HC=0x04 ABS=0x2C

        Mean:            HC=0x02 ABS=0x7F

        End-0.5*tCK:    HC=0x03 ABS=0x2C

        Final:          HC=0x03 ABS=0x2C

BYTE 4:

        Start:          HC=0x01 ABS=0x00

        End:            HC=0x04 ABS=0x44

        Mean:            HC=0x02 ABS=0x61

        End-0.5*tCK:    HC=0x03 ABS=0x44

        Final:          HC=0x03 ABS=0x44

BYTE 5:

        Start:          HC=0x01 ABS=0x6C

        End:            HC=0x04 ABS=0x44

        Mean:            HC=0x03 ABS=0x18

        End-0.5*tCK:    HC=0x03 ABS=0x44

        Final:          HC=0x03 ABS=0x44

BYTE 6:

        Start:          HC=0x01 ABS=0x4C

        End:            HC=0x04 ABS=0x14

        Mean:            HC=0x02 ABS=0x6F

        End-0.5*tCK:    HC=0x03 ABS=0x14

        Final:          HC=0x03 ABS=0x14

BYTE 7:

        Start:          HC=0x01 ABS=0x00

        End:            HC=0x04 ABS=0x40

        Mean:            HC=0x02 ABS=0x5F

        End-0.5*tCK:    HC=0x03 ABS=0x40

        Final:          HC=0x03 ABS=0x40


DQS calibration MMDC0 MPDGCTRL0 = 0x433C0348, MPDGCTRL1 = 0x032C0328

DQS calibration MMDC1 MPDGCTRL0 = 0x43440344, MPDGCTRL1 = 0x03400314


Note: Array result[] holds the DRAM test result of each byte.

      0: test pass.  1: test fail

      4 bits respresent the result of 1 byte.

      result 00000001:byte 0 fail.

      result 00000011:byte 0, 1 fail.

Starting Read calibration...

ABS_OFFSET=0x00000000  result[00]=0x11111111

ABS_OFFSET=0x04040404  result[01]=0x11111111

ABS_OFFSET=0x08080808  result[02]=0x11111111

ABS_OFFSET=0x0C0C0C0C  result[03]=0x11111111

ABS_OFFSET=0x10101010  result[04]=0x11011111

ABS_OFFSET=0x14141414  result[05]=0x00011001

ABS_OFFSET=0x18181818  result[06]=0x00001000

ABS_OFFSET=0x1C1C1C1C  result[07]=0x00000000

ABS_OFFSET=0x20202020  result[08]=0x00000000

ABS_OFFSET=0x24242424  result[09]=0x00000000

ABS_OFFSET=0x28282828  result[0A]=0x00000000

ABS_OFFSET=0x2C2C2C2C  result[0B]=0x00000000

ABS_OFFSET=0x30303030  result[0C]=0x00000000

ABS_OFFSET=0x34343434  result[0D]=0x00000000

ABS_OFFSET=0x38383838  result[0E]=0x00000000

ABS_OFFSET=0x3C3C3C3C  result[0F]=0x00000000

ABS_OFFSET=0x40404040  result[10]=0x00000000

ABS_OFFSET=0x44444444  result[11]=0x00000000

ABS_OFFSET=0x48484848  result[12]=0x00000000

ABS_OFFSET=0x4C4C4C4C  result[13]=0x00000000

ABS_OFFSET=0x50505050  result[14]=0x01000100

ABS_OFFSET=0x54545454  result[15]=0x11000111

ABS_OFFSET=0x58585858  result[16]=0x11100111

ABS_OFFSET=0x5C5C5C5C  result[17]=0x11101111

ABS_OFFSET=0x60606060  result[18]=0x11111111

ABS_OFFSET=0x64646464  result[19]=0x11111111

ABS_OFFSET=0x68686868  result[1A]=0x11111111

ABS_OFFSET=0x6C6C6C6C  result[1B]=0x11111111

ABS_OFFSET=0x70707070  result[1C]=0x11111111

ABS_OFFSET=0x74747474  result[1D]=0x11111111

ABS_OFFSET=0x78787878  result[1E]=0x11111111

ABS_OFFSET=0x7C7C7C7C  result[1F]=0x11111111


MMDC0 MPRDDLCTL = 0x3A303234, MMDC1 MPRDDLCTL = 0x3230323A


Starting Write calibration...

ABS_OFFSET=0x00000000  result[00]=0x11111111

ABS_OFFSET=0x04040404  result[01]=0x10111111

ABS_OFFSET=0x08080808  result[02]=0x10111111

ABS_OFFSET=0x0C0C0C0C  result[03]=0x10110111

ABS_OFFSET=0x10101010  result[04]=0x10100010

ABS_OFFSET=0x14141414  result[05]=0x00100010

ABS_OFFSET=0x18181818  result[06]=0x00100000

ABS_OFFSET=0x1C1C1C1C  result[07]=0x00100000

ABS_OFFSET=0x20202020  result[08]=0x00000000

ABS_OFFSET=0x24242424  result[09]=0x00000000

ABS_OFFSET=0x28282828  result[0A]=0x00000000

ABS_OFFSET=0x2C2C2C2C  result[0B]=0x00000000

ABS_OFFSET=0x30303030  result[0C]=0x00000000

ABS_OFFSET=0x34343434  result[0D]=0x00000000

ABS_OFFSET=0x38383838  result[0E]=0x00000000

ABS_OFFSET=0x3C3C3C3C  result[0F]=0x00000000

ABS_OFFSET=0x40404040  result[10]=0x00000000

ABS_OFFSET=0x44444444  result[11]=0x00000000

ABS_OFFSET=0x48484848  result[12]=0x00000000

ABS_OFFSET=0x4C4C4C4C  result[13]=0x00000000

ABS_OFFSET=0x50505050  result[14]=0x00000000

ABS_OFFSET=0x54545454  result[15]=0x00000000

ABS_OFFSET=0x58585858  result[16]=0x00000000

ABS_OFFSET=0x5C5C5C5C  result[17]=0x00000000

ABS_OFFSET=0x60606060  result[18]=0x00000000

ABS_OFFSET=0x64646464  result[19]=0x00000000

ABS_OFFSET=0x68686868  result[1A]=0x00000101

ABS_OFFSET=0x6C6C6C6C  result[1B]=0x01001111

ABS_OFFSET=0x70707070  result[1C]=0x01001111

ABS_OFFSET=0x74747474  result[1D]=0x11001111

ABS_OFFSET=0x78787878  result[1E]=0x11011111

ABS_OFFSET=0x7C7C7C7C  result[1F]=0x11111111


MMDC0 MPWRDLCTL = 0x3A3A403A,MMDC1 MPWRDLCTL = 0x42364C42


  MMDC registers updated from calibration


  Read DQS Gating calibration

  MPDGCTRL0 PHY0 (0x021b083c) = 0x433C0348

  MPDGCTRL1 PHY0 (0x021b0840) = 0x032C0328

  MPDGCTRL0 PHY1 (0x021b483c) = 0x43440344

  MPDGCTRL1 PHY1 (0x021b4840) = 0x03400314

 

  Read calibration

  MPRDDLCTL PHY0 (0x021b0848) = 0x3A303234

  MPRDDLCTL PHY1 (0x021b4848) = 0x3230323A

 

  Write calibration

  MPWRDLCTL PHY0 (0x021b0850) = 0x3A3A403A

  MPWRDLCTL PHY1 (0x021b4850) = 0x42364C42

 

The DDR stress test can run with an incrementing frequency or at a static freq

To run at a static freq, simply set the start freq and end freq to the same value

Would you like to run the DDR Stress Test (y/n)?

 

Enter desired START freq (135 to 672 MHz), then hit enter.

Note: DDR3 minimum is ~333MHz, do not recommend to go too much below this.

528

  The freq you entered was: 528

 

Enter desired END freq (135 to 672 MHz), then hit enter.

Make sure this is equal to or greater than start freq

650

  The freq you entered was: 650

Beginning stress test

loop: 1

DDR Freq: 528 MHz

t0.1: data is addr test

t0: memcpy10 SSN x64 test

t1: memcpy8 SSN x64 test

t2: byte-wise SSN x64 test

t3: memcpy11 random pattern test

t4: IRAM_to_DDRv2 test

t5: IRAM_to_DDRv1 test

t6: read noise walking ones and zeros test

Outcomes