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Ethernet component clock gating bug

Question asked by Peter Liedholm on Nov 19, 2014

Hi

When running init method of ethernet LDD, a hard fault occurs due to missing clock gating of a port.

This can be reproduced easily and a test program is attached.

 

Processor Expert Driver Suite 10.4.1 was used together with IAR 7.30.1.

 

Regards

/Peter

 

  /* THIS WILL FAIL IN ETH1 LINE 231 DUE TO PORT CLOCK NOT SET */

  /* The following two lines fixes it if uncommented */

//  /* SIM_SCGC5: PORTB=1 */

//  SIM_SCGC5 |= SIM_SCGC5_PORTB_MASK;

  device = ETH1_Init(NULL);

 

Build.jpgDebuggerAtError.jpgDebuggerAtInstructionCausingError.jpg

Original Attachment has been moved to: ETH_K64.zip

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