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MCUinit.c: Wait until PLL is locked...

Question asked by Doug Paulsen on Nov 19, 2014
Latest reply on Nov 19, 2014 by TomE

Greetings: 

 

We have a MCF51AC256AC based project which is exhibiting a disconcerting tendency to fail to achieve PLL lock.

 

This is a Codewarrior 6.3 project and uses the Device Initialization feature to create a MCUinit.c file.  When starting up, MCU_init() executes but has a tendency to not a execute beyond the while(!MCGSC_LOCK) at the end of this code snippet:

  /*  System clock initialization */

  if (*(unsigned char*far)65470 != 255) { /* Test if the device trim value is stored on the specified address */

    MCGTRM = *(unsigned char*far)65470; /* Initialize MCGTRM register from a non volatile memory */

    MCGSC = *(unsigned char*far)1022;  /* Initialize MCGSC register from a non volatile memory */

  }

  /* MCGC2: BDIV=0,RANGE=1,HGO=1,LP=0,EREFS=1,ERCLKEN=1,EREFSTEN=0 */

  MCGC2 = 54;                          /* Set MCGC2 register */

  /* MCGC3: DIV32=1 */

  MCGC3 |= (unsigned char)16;                     

  /* MCGC1: CLKS=2,RDIV=2,IREFS=0,IRCLKEN=0,IREFSTEN=0 */

  MCGC1 = 144;                         /* Set MCGC1 register */

  /* MCGC3: LOLIE=0,PLLS=0,CME=0,DIV32=1,VDIV=8 */

  MCGC3 = 24;                          /* Set MCGC3 register */

  /* MCGC4: DMX32=0,DRST_DRS=0 */

  MCGC4 = 0;                           /* Set MCGC4 register */

  while(!MCGSC_OSCINIT) {              /* Wait until external reference is stable */

   SRS = 0;                            /* Reset watchdog counter */

  }

  while(MCGSC_IREFST) {                /* Wait until external reference is selected */

   SRS = 0;                            /* Reset watchdog counter */

  }

  while((MCGSC & 12) != 8) {           /* Wait until external clock is selected as a bus clock reference */

   SRS = 0;                            /* Reset watchdog counter */

  }

  /* MCGC2: BDIV=0,RANGE=1,HGO=1,LP=1,EREFS=1,ERCLKEN=1,EREFSTEN=0 */

  MCGC2 = 62;                          /* Set MCGC2 register */

  /* MCGC1: CLKS=2,RDIV=3,IREFS=0,IRCLKEN=0,IREFSTEN=0 */

  MCGC1 = 152;                         /* Set MCGC1 register */

  /* MCGC3: LOLIE=0,PLLS=0,CME=0,DIV32=0,VDIV=8 */

  MCGC3 = 8;                           /* Set MCGC3 register */

  /* MCGC3: LOLIE=0,PLLS=1,CME=0,DIV32=0,VDIV=8 */

  MCGC3 = 72;                          /* Set MCGC3 register */

  while(!MCGSC_PLLST) {                /* Wait until PLL is selected */

   SRS = 0;                            /* Reset watchdog counter */

  }

  /* MCGC2: LP=0 */

  MCGC2 &= (unsigned char)~8;                    

  while(!MCGSC_LOCK) {                 /* Wait until PLL is locked */

   SRS = 0;                            /* Reset watchdog counter */

  }

 

To decode the above, the project is defined with an external 9.8304 MHz CPU clock.  PLL mode PEE is selected with a reference clock divider auto selecting to 8 and the PLL multiplier factor auto selecting to 32.  This yields a 39.3216 MHz PLL output clock frequency and ultimately a 19.660 MHz internal bus frequency.  Why so fast?  Well, this yields a critical 4.9 MHz PWM output which in turn clocks a peripheral chip.

 

I have observed the occasional "while(!MCGSC_LOCK)" wait during development, which I had (hopefully) attributed to prototype hardware and/or BDM debugger interaction.  Most distressingly, the PLL lock wait continues to appear now the project is in its free standing phase running on production hardware.

 

Any ideas why PLL lock seems to be difficult to achieve?  This project a next generation based on a HCS08 project where the identical setup has been used without issue.  Of course this is different hardware.

In the course of power consumption testing, we did find the power consumption of the MCF51AC256 goes way, way up when running in PLL mode (a point not identified in the documentation, so beware!).  Are there other drawbacks to PLL mode use in this chip?

 

Thanks for any thoughts or suggestions,

Doug

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