Page 9 of Rev4 of Document KL02P20M48SF0 states:
2. The reset pin only contains an active pull down device when configured as the RESET signal or as a GPIO. When
configured as a GPIO output, it acts as a pseudo open drain output.
My question is:
Why does this state that the reset pin contains an active pull down device? The reset for this chip is active low, so shouldn't the chip contain a pullup resistor?
Or, am I reading this incorrectly and there is both a pullup resistor and an optional pulldown device?