Paul DeRocco

Bad design: no mask register for port interrupts

Discussion created by Paul DeRocco on Nov 14, 2014
Latest reply on Nov 18, 2014 by Chris Brown

I think in any future MCU series, Freescale needs to redesign the way port pin interrupts are handled slightly. What's missing is a 32-bit mask register. The only way you can prevent a request from a particular pin from being recognized is to disable it in the PORTx_PCRn register, but that's not the same thing as masking it because it discards any pending edge-detected interrupt. Also, you can't use the edge-detection logic to turn a pulse into a static level, and then poll it in software.


Instead of ORing the PORTx_ISFR bits together into the single NVIC input, PORTx_ISFR should be ANDed with a new 32-bit mask register at offset 0xA4 and then ORed into the NVIC. This would separate the definition of what constitutes a request (high level, low level, rising edge, falling edge, either edge), and the latching of edge-triggered interrupts, from the masking or unmasking of the interrupt. This would seem to me to be basic interrupt logic design--I'm surprised the designers got it wrong.


This can be fixed in software, but it's a bunch of work. For level sensitive interrupts, switch the individual pins to Disabled to mask them, and then switch them back to Logic 0 or Logic 1 to unmask them. For edge-sensitive interrupts, leave them all enabled, and have the interrupt handler "handle" those that are masked in software by setting deferred request bits for the masked interrupts in software, which would be invoked whenever they are later unmasked. Pretty ugly.