Kinetis SAI Support for TDM?

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Kinetis SAI Support for TDM?

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eli_hughes
Contributor V

I think the SAI section for the K64F (and variants) needs some clarification with regards to the Frame Sync With.  The prose in the manual claims TDM support, but I cannot see from the manual how you can get a proper frame sync as you cannot set the width to a large enough value.

I don't think the TDM capability based upon what is in the register description.  For example,  let’s say I am trying to configure for an 8-channel TDM (for example a cirrus logic CS5368).   This requires a word length of 32-bits and 8 words per frame.   This means that the frame sync should be active for 4 words (128 bits).

Let’s consider the setup for a receiver.  I am assume, BCLK MCLK and FRAME SYNC are generated *externally* by an ADC.

RCR4 setups up the frame sync.   I can set FRSZ (bits 20-16) as 7 (gives me 8 words per frame).

The problem is in SYWD. (Bits 12-8).  It claims that I can on set the value in  bits and the width cannot be longer than the 1st word of the frame.   This is not an issue for I2S or PCM.  It appears that you cannot support TDM with the SAI.   The frame sync must be able to a width of ½ of the total number of words. 4 words (128 bits).

Can someone confirm this?

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Kan_Li
NXP TechSupport
NXP TechSupport

I am sorry , but referring to the data sheet of CS5368, TDM format just needs a FS of word wide at max, it is not what you mentioned "a width of ½ of the total number of words. 4 words (128 bits)." is there any misunderstanding?

Please kindly refer to page 26 of http://www.go-gddq.com/downlocal/cs/CS5368.pdf for details.

Untitled.png


Have a great day,
Kan

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386 Views
eli_hughes
Contributor V

Kan:

Here is the diagram I was was refering to:

(Page 23 of the datasheet http://www.cirrus.com/en/pubs/proDatasheet/CS5368_F5.pdf)

TDM.png

It looks like your picture is from a different version.   In the picture I have attached,  it shows the frame sync 4 words wide.

I am getting a PCB in a couple weeks to actually probe to verify the timing..... Hopefully I can make it work@

A quick question though....   If the SAI is operating in TDM Slave,  does it actually care about the width of the FS pulse?   I.E.  Would it only look for a rising edge to start a new frame?

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Kan_Li
NXP TechSupport
NXP TechSupport

RM says"

The frame sync signal is used to indicate the start of each frame. A valid frame sync

requires a rising edge (if active high) or falling edge (if active low) to be detected and the

transmitter or receiver cannot be busy with a previous frame. A valid frame sync is also

ignored (slave mode) or not generated (master mode) for the first four bit clock cycles

after enabling the transmitter or receiver."

so in my understanding,  I think this signal should be a edge signal to SAI module.


Have a great day,
Kan

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