My customer is facing the issue around i.MX6 ESAI TDM data transfer.
Please find the attached file for the details.
The issue is that TDM slot data could be misaligned when bit clock is higher than 20.8MHz.
In my understanding, the bit clock of i.MX6S ESAI can be up to 33MHz.
Is it true?
The customer has a doubt whether ESAI can work fine in such situation(bit clock>20.8MHz, 8slot TDM).
Once i posted same question to TIC and the answer was that it may be caused by silicon erratum ERR008000.
Is it sure?